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Embedded Computing

Katana®752i

Real-Time Processing Blade

KatanaQp

  • PowerPC 750GX processor running at up to 1GHz
  • cPSB Node (PICMG 2.16, Dual 1000 BaseT)
  • cPCI peripheral functionality
  • Dual PMC / PTMC expansion sites
  • System Management Bus (PICMG 2.9) with IPMI peripheral controller
  • Up to 2 GByte DDR ECC SDRAM in SODIMM package
  • Up to 128MB Linear Flash
  • Real-Time Clock with supercap backup
  • Dual 10/100/1000 BaseT Ethernet with front bezel access
  • VxWorks and CG Linux support
  • RoHS/WEEE compliant configuration available
  • Quality assured by over 35 years of design experience and a TL-9000 and ISO 9001:2000 certified quality management system. (FM 26789)
Board Photograph

Emerson’s Katana752i is a real-time processing blade in a standard sing-slot CompactPCI Packet Switching Backplane (cPSB) formfactor. It’s powered by a PowerPC 750GX processor and a full complement of I/O for communications applications. The combination of this powerful on-card functionality with the flexibility of dual PMC/PTMC sites makes the board ideal for a variety of functions including signaling blade, media gateway blade, real-time control blade, traffic processor, or line-card.

Communications applications are rapidly converging on packet-based switch fabric system architectures. Katana752i’s design is ideally suited to the packet paradigm. To support this paradigm, the blade is fully compliant with the PICMG 2.16 cPSB specification. While technology is rapidly converging on packet networks for the majority of data transport, many applications require systems to link more traditional TDM-based networks to the packet networks. To help facilitate this, the Katana752i supports an optional timeslot interchanger to interconnect the PTMC expansion sites with a local CTbus as well as provide an interface to the H.110 system backplane CTbus.

As systems designs become more complex, system management becomes more important. Katana752i implements a System Management Bus (SMB). It also fully supports the Intelligent Platform Management Interface (IPMI or PICMG 2.9) for standards-based system management.

Using an off-the-shelf processor blade saves you time-to-market by allowing you to focus your engineering efforts on the key value-add portions of the system without spending time and effort on the processor design and testing. A processor subsystem blade also lowers you lifetime cost of ownership by providing an easy upgrade path, and protecting you from obsolescence issues.

Processor
PowerPC 750GX processor running at up to 1GHz
  • 64-bit data bus
  • 32-bit address bus
  • 32K I / 32K D L1 Cache
  • 1MB L2 Cache with ECC
System Controller
Marvell Discovery III system controller
  • PCI bridge
  • 2 GbE interfaces to 2.16 backplane
  • Dual 10/100/1000 BaseTx debug interface (front bezel access)
  • I2C interface
  • SDRAM controller
  • Four timer/counters, each selectable as a counter or timer
  • 32-bit watchdog timer
  • 4 IDMA Controllers
  • 2 baud rate generators
  • Reset
Memory
SDRAM
  • Up to 512 MByte, 1 or 2 GByte DDR SDRAM with Error Checking and Correction (ECC)
  • Dual data rate operation clocked at 133MHz
  • Modular and upgradeable 200-pin SODIMM packaging
User Flash
  • Up to 128 MByte Flash configurations
  • True Flash File System™ (TFFS) support under VxWorks
  • Flash Architecture NOR
Serial EEPROM
  • 64KB Serial EEPROM on I2C bus for configuration data
Expansion
PMC/PTMC
  • PCI Mezzanine Card (PMC) interface complies with IEEE 1386 and 1386.1
  • Two PMC sites PCI 2.2 compliant, 32-bit, 33/66 MHz PCI Bus interface
  • PMC site can be configured as a Monarch with a ProcessorPMC module installed
  • 64 user I/O pins routed to cPCI J3 and J5
  • Optional RMII / PHY support from Jx3 connector to cPCI J5 connector
  • PCI Telephony Mezzanine Card (PTMC) complian
  • Optional T8110 Timeslot Interchanger to route CTBus between PTMC sites and the backplane H.110 TDM bus
  • CTBus clocks routed from J4 for systems with H.110 telecom clocks accepts 2 singlewide or 1 double-wide PMC module
  • Accepts 2 single-wide or one double-wide PMC Modules
Blade I/O
Ethernet
  • Embedded System Area Network (ESAN)
    • CompactPCI Packet Switching Backplane (cPSB – PICMG 2.16) Peripheral node/dual link
    • Dual 10/100/1000BaseT interfaces via on-card Marvell Discovery III System Controller
  • Single 10/100BaseT maintenance Ethernet port via front bezel
PCI
  • cPCI embedded peripheral functionality
  • Local PCI 2.2 bus between PMC sites and Discovery III system controller
  • 32-bit operation
  • 33/66MHz operation
Serial I/O
  • One console serial port
  • EIA-232 signal levels
  • Micro-DB9 connectors with front panel access
JTAG/COP
  • A single JTAG/COP interface shared by 3 daisychained processors
    • IEEE 1149.1 compatible
    • Access to internal processor scan chains for debug
    • Serial connection to processor core for emulator support
  • JTAG/COP interface for on-card PLDs
I2C
  • Master/Slave I2C bus connecting
    • Serial EEPROMs
    • Real-time clock device
    • IPMI controller and sensors
    • Processor I2C interface to IPMI connector
IPMI
  • System Management Bus (SMB) as defined by CompactPCI System Management Specification (PICMG 2.9)
  • Supports Intelligent Platform Management Interface (IPMI) Version 1.5 and Intelligent Platform Management Bus (IPMB) Version 1.0
  • Driven by Zircon Peripheral Management device from QLogic
  • IPMB interface to backplane (PICMG 2.9)
  • Two local I2C interfaces
    • Master/slave interface for processor communications
    • Master-only interface for accessing the two IPMI readonly memory (ROM) and temperature sensor readings
  • Uses Zircon PM GPIO for
    • Watchdog timer expiration output
    • GPIO to 750GX processors
    • IPMI reset control
    • Temperature sensor interrupts
PTMC
  • CTbus TDM channels are optionally routed to/from PTMC sites, through a timeslot interchanger to/from the J4 H.110 CTbus.
  • CTbus clocks are routed from J4 H.110 CTbus to the PMC sites
LEDs and Switches
  • 4 development user-programmable surface mount LEDs per processor complex
  • Seven front panel LEDs
  • cPSB1 and cPSB2 Activity and Link
  • Power/fault status
  • Hot Swap
  • Recessed front panel reset switch
Physical Characteristics
  • cPSB PICMG 2.16 formfactor
  • Dimensions: 9.19" W x 6.30" D x <0.80" H (233.25mm x 160mm x <20.32mm)
  • Power requirements: 30W Max
  • Operating range: 0° to 55° C, 5-95% relative
Agency Compliance
  • UL/CSA/IEC60950
  • FCC Part 15, (US)
  • ICES 003, (Canada)
  • EN 55022
  • EN 55024
  • EN 300 386
  • NEBS: Applicable sections of Telcordia GR-63 and GR-1089
Software Support
  • U-boot monitor with power-on self test
  • Board support package for VxWorks 5.5/Tornado 2.2 (One VxWorks runtime license required per processor complex)
  • Board support package for Linux
  • Carrier Grade Linux support
    • MontaVista CGE
    • Wind River PNE LE
Related Products
Block Digram

7/07