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Embedded Computing

Katana®750i

Real-Time Processing Blade

KatanaQp

  • PowerPC 750FX processor running at 800MHz
  • cPSB Node (PICMG 2.16, Dual 1000BaseT)
  • Dual PMC expansion sites
  • System Management Bus (PICMG 2.9) w/ IPMI Peripheral Controller
  • Up to 1GByte DDR ECC SDRAM in SODIMM package
  • Up to 128MB linear Flash
  • Real-Time Clock with supercap backup
  • 10/100BaseT Ethernet with front access
  • 64K Serial EEPROM for nonvolatile storage
  • VxWorks™ BSP
  • TimeSys™ real-time Linux SDK
  • RoHS/WEEE compliant configuration available
  • Quality assured by over 35 years of design experience and a TL-9000 and ISO 9001:2000 certified quality management system. (FM 26789)
Board Photograph

Emerson’s Katana750i is real-time processing blade in a standard single-slot CompactPCI Packet Switched Backplane (cPSB) formfactor. It’s powered by a PowerPC 750FX processor and a full complement of I/O for communications applications. The combination of this powerful on-card functionality with the flexibility of dual PMC sites makes the board ideal for a variety of functions including signaling blade, real-time control blade, traffic processor, or line card.

Communications applications are rapidly converging on packet-based switch fabric system architectures. Katana750i’s design is ideally suited to the packet paradigm. To support this paradigm, the blade is fully compliant with the PICMG 2.16 cPSB specification. While technology is rapidly converging on packet networks for the majority of data transport, many applications require systems to link more traditional TDM-based networks to the packet networks. To help facilitate this, the Katana750i supports an optional timeslot interchanger to interconnect the PTMC expansion sites with a local CTbus as well as provide an interface to the H.110 system backplane CTbus.

As systems designs become more complex, system management becomes more important. Katana750i implements a System Management Bus (SMB). It also fully supports the Intelligent Platform Management Interface (IPMI or PICMG 2.9) for standards-based system management.

Using an off-the-shelf processor blade saves you time-to-market by allowing you to focus your engineering efforts on the key value-add portions of the system without spending time and effort on the processor design and testing. A processor subsystem blade also lowers your lifetime cost of ownership by providing an easy upgrade path, and protecting you from obsolescence issues.

Processor
  • PowerPC 750FX processor running at 800MHz
  • 64-bit data bus
  • 32-bit address bus
  • 32K I / 32K D L1 Cache
  • 512K L2 Cache with ECC
System Controller
  • Marvell MV64360 system controller
  • PCI bridge
  • 2 GbE interfaces to 2.16 backplane
  • Single 10/100 BaseTx debug interface (front bezel access)
  • I2C interface
  • SDRAM controller
  • Eight timer/counters, each selectable as a counter or timer
  • 32-bit watchdog timer
  • 4 IDMA Controllers
  • 2 baud rate generators
  • Reset
Memory
DDR SDRAM
  • 256, 512 MByte, 1or 2 GByte SDRAM with Error Checking and Correction (ECC)
  • Dual data rate operation clocked at 133MHz
  • Modular and upgradeable 200-pin SODIMM packaging
User Flash
  • 32, 64 or 128 MByte Flash configurations
  • True Flash File System™ (TFFS) support under VxWorks
  • Flash Architecture NOR
Serial EEPROM
  • 64KB Serial EEPROM on I2C bus for configuration data
Expansion
PMC/PTMC
  • PCI Mezzanine Card (PMC) interface complies with IEEE 1386 and 1386.1
  • Two PMC sites PCI 2.2 compliant, 32-bit, 33/66 MHz PCI Bus interface
  • PMC site can be configured as a Monarch with a ProcessorPMC module installed
  • 64 user I/O pins routed to cPCI J3 and J5
  • Optional RMII / PHY support from Jx3 connector to cPCI J5 connector
  • PCI Telephony Mezzanine Card (PTMC) compliant
  • Optional T8110 Timeslot Interchanger to route CTBus between PTMC sites and the backplane H.110 TDM bus
  • CTBus clocks routed from J4 for systems with H.110 telecom clocks
  • Accepts 2 single-wide or 1 double-wide PMC module
Blade I/O
Ethernet
  • Embedded System Area Network (ESAN)
    • CompactPCI Packet Switching Backplane (cPSB – PICMG 2.16) Peripheral node/dual link
    • Dual 10/100/1000BaseT interfaces via on-card Marvell Discovery II System Controller
  • Single 10/100BaseT maintenance Ethernet port via front bezel
PCI
  • Local PCI 2.2 bus between PMC sites and Discovery II system controller
  • 32-bit operation
  • 33/66MHz operation
I2C
  • Master/Slave I2C bus connecting
    • Serial EEPROMs
    • Real-time clock device
    • IPMI controller and sensors
    • Processor I2C interface to IPMI connector
Serial I/O
  • One console serial port
  • EIA-232 signal levels
  • Micro-DB9 connectors with front panel access
JTAG/COP
  • JTAG/COP debug interface
    • IEEE 1149.1 compatible
    • Access to internal processor scan chains for debug
    • Serial connection to processor core for emulator support
  • JTAG/COP interface for on-card PLDs
IPMI
  • System Management Bus (SMB) as defined by CompactPCI System Management Specification (PICMG 2.9)
  • Supports Intelligent Platform Management Interface (IPMI) Version 1.5 and Intelligent Platform Management Bus (IPMB) Version 1.0
  • Driven by Zircon Peripheral Management device from QLogic
    • Remote shutdown
    • Remote reset
    • Payload Power Monitor
    • Temp monitor
    • FRU data structure
PTMC
  • CTbus TDM channels are optionally routed to/from PTMC sites, through a timeslot interchanger to/from the J4 H.110 CTbus.
  • CTbus clocks are routed from J4 H.110 CTbus to the PMC site
LEDs and Switches
  • 4 development user-programmable surface mount LEDs
  • Front panel Ethernet Activity and Link LEDs
  • cPSB1 and cPSB2 Activity and Link front panel LEDs
  • Power/fault front panel status LEDs
  • Hot Swap front panel LED
  • Recessed front panel rest switch
Physical Characteristics
  • cPSB PICMG 2.16 formfactor
  • Dimensions: 9.19" W x 6.30" D x <0.80" H (233.25mm x 160mm x <20.32mm)
  • Power requirements: 10W estimated typical
  • Operating range: 0° to 55° C, 5-95% relative humidity (non-condensing) to meet or exceed NEBS Telcordia GR-63 specification.
Agency Compliance
  • UL/CSA/IEC60950
  • FCC Part 15 (US)
  • ICES 003 (Canada)
  • EN 55022
  • EN300 386
  • EN 55024
  • Applicable sections of NEBS: Telcordia GR1089 and GR-63
Software Support
  • PPCBoot bootloader with power-on self test
  • TimeSys real-time Linux Software Development Kit (SDK)
  • Board support package for VxWorks 5.5/Tornado 2.2
  • Reference kernel port for GPL Linux
  • Carrier Grade Linux Support
    • MontaVista CGE
    • Wind River PNE LE
Related Products
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